https://wiki-ext.aps.anl.gov/ccd/api.php?action=feedcontributions&feedformat=atom&user=Weizeor 2026-06-10T17:52:20Z User contributions MediaWiki 1.36.1 https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=87 2013-01-24T14:36:42Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Immersion chiller probe on detector head.<br /> Go back and switch conflat cupper gasket to rubber gasket.<br /> 2. Pump down, Cool down, turn on, and take dark images at various exposure times.<br /> <br /> Verify that dark images get brighter with longer exposure times.<br /> Verify that the noise is at the expected level.<br /> 3. Take some optical images.<br /> Generate a photon transfer curve.<br /> 4. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 5. Software development<br /> Area detector, data reduction, user interface.....<br /> 6. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 7. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 8. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> <br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> 4. Wired up two Thermocouples so I can monitor internal temperature<br /> <br /> I hooked up the CCD thermocouple and the thermocouple on the warm side of the clock module.<br /> <br /> 5. Install Immersion chiller probe on detector head<br /> <br /> Before installing the immersion chiller I changed a rubber conflat gasket to a metal one.<br /> I though this might be the cause of a leak, but I now realize that the rubber gasket was a thermal break with the copper block.<br /> I will have to go back and put back in a rubber conflat gasket (John Hoyte says that they have some)<br /> <br /> 6. Wire up equipment protection interlock and test it out<br /> <br /> This turns of the detector power if the detector head goes over -10degree C, and it turns off the chiller if the pressure goes above .001 mbar.<br /> <br /> 7. Pump down, Cool down, and turn on detector and take fCRIC clamp images<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=86 2013-01-24T14:35:05Z

<p>Weizeor: /* With Detector Head from LBNL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Immersion chiller probe on detector head.<br /> Go back and switch conflat cupper gasket to rubber gasket.<br /> 2. Take dark images<br /> 3. Put a vacuum on the detector, cool it down, power it up, take some clamp images then dark images.<br /> Look at the noise of the clamp images.<br /> Verify that dark images get brighter with longer exposure times.<br /> Verify that the noise is at the expected level.<br /> 5. Take some optical images.<br /> Generate a photon transfer curve.<br /> 6. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 7. Software development<br /> Area detector, data reduction, user interface.....<br /> 8. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 9. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 10. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> <br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> 4. Wired up two Thermocouples so I can monitor internal temperature<br /> <br /> I hooked up the CCD thermocouple and the thermocouple on the warm side of the clock module.<br /> <br /> 5. Install Immersion chiller probe on detector head<br /> <br /> Before installing the immersion chiller I changed a rubber conflat gasket to a metal one.<br /> I though this might be the cause of a leak, but I now realize that the rubber gasket was a thermal break with the copper block.<br /> I will have to go back and put back in a rubber conflat gasket (John Hoyte says that they have some)<br /> <br /> 6. Wire up equipment protection interlock and test it out<br /> <br /> This turns of the detector power if the detector head goes over -10degree C, and it turns off the chiller if the pressure goes above .001 mbar.<br /> <br /> 7. Pump down, Cool down, and turn on detector and take fCRIC clamp images<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=85 2013-01-24T14:32:02Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Immersion chiller probe on detector head.<br /> Go back and switch conflat cupper gasket to rubber gasket.<br /> 2. Take dark images<br /> 3. Put a vacuum on the detector, cool it down, power it up, take some clamp images then dark images.<br /> Look at the noise of the clamp images.<br /> Verify that dark images get brighter with longer exposure times.<br /> Verify that the noise is at the expected level.<br /> 5. Take some optical images.<br /> Generate a photon transfer curve.<br /> 6. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 7. Software development<br /> Area detector, data reduction, user interface.....<br /> 8. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 9. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 10. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> 4. Wired up two Thermocouples so I can monitor internal temperature<br /> <br /> I hooked up the CCD thermocouple and the thermocouple on the warm side of the clock module.<br /> <br /> 5. Install Immersion chiller probe on detector head<br /> <br /> Before installing the immersion chiller I changed a rubber conflat gasket to a metal one.<br /> I though this might be the cause of a leak, but I now realize that the rubber gasket was a thermal break with the copper block.<br /> I will have to go back and put back in a rubber conflat gasket (John Hoyte says that they have some)<br /> <br /> <br /> Special Tools are on hand now.<br /> 6. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> <br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=84 2013-01-24T14:30:37Z

<p>Weizeor: /* COMPLETED TASK */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 2. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 3. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 4. Put a vacuum on the detector, cool it down, power it up, take some clamp images then dark images.<br /> Look at the noise of the clamp images.<br /> Verify that dark images get brighter with longer exposure times.<br /> Verify that the noise is at the expected level.<br /> 5. Take some optical images.<br /> Generate a photon transfer curve.<br /> 6. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 7. Software development<br /> Area detector, data reduction, user interface.....<br /> 8. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 9. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 10. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> 4. Wired up two Thermocouples so I can monitor internal temperature<br /> <br /> I hooked up the CCD thermocouple and the thermocouple on the warm side of the clock module.<br /> <br /> 5. Install Immersion chiller probe on detector head<br /> <br /> Before installing the immersion chiller I changed a rubber conflat gasket to a metal one.<br /> I though this might be the cause of a leak, but I now realize that the rubber gasket was a thermal break with the copper block.<br /> I will have to go back and put back in a rubber conflat gasket (John Hoyte says that they have some)<br /> <br /> <br /> Special Tools are on hand now.<br /> 6. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> <br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=83 2013-01-24T14:24:56Z

<p>Weizeor: /* TO DO */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 2. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 3. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 4. Put a vacuum on the detector, cool it down, power it up, take some clamp images then dark images.<br /> Look at the noise of the clamp images.<br /> Verify that dark images get brighter with longer exposure times.<br /> Verify that the noise is at the expected level.<br /> 5. Take some optical images.<br /> Generate a photon transfer curve.<br /> 6. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 7. Software development<br /> Area detector, data reduction, user interface.....<br /> 8. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 9. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 10. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=82 2013-01-18T22:49:13Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 2. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 3. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 4. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 5. Take some optical images.<br /> Generate a photon transfer curve.<br /> 6. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 7. Software development<br /> Area detector, data reduction, user interface.....<br /> 8. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 9. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 10. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=81 2013-01-18T22:48:40Z

<p>Weizeor: /* With Detector Head from LBNL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Pump down Detector<br /> Not getting a good vacuum yet!!<br /> 2. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 3. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Pump down Detector<br /> <br /> Vacuum would get down to 5.0 e -1 mbar and then start going up.<br /> Change all o-rings and change conflat rubber gasket with metal gasket.<br /> Still doning same think.<br /> John B and Chris P pumped with larger ruffing pump looking for leak.<br /> Got to lower vacuum and could not find leak.<br /> When they got done I hooked up turbo pump and it got to 5.0 e-2 mbar and kept going down.<br /> So maybe it was a vertual leak that just needed to be pumped on??<br /> Will let it pump over the weekend and see if we get to 1.0 e-5 mbar.<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=80 2013-01-17T21:48:59Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Pump down Detector<br /> Not getting a good vacuum yet!!<br /> 2. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 3. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=79 2013-01-17T21:48:04Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Pump down Detector<br /> <br /> 2. Wire up Thermocouples so I can monitor internal temperature<br /> <br /> 3. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=78 2013-01-16T17:48:42Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 3. Install Immersion chiller probe on detector head.<br /> Special Tools are on hand now.<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=77 2013-01-16T17:47:55Z

<p>Weizeor: /* With Detector Head from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=76 2013-01-16T17:47:29Z

<p>Weizeor: /* COMPLETED TASK */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL ===<br /> 1. Ring out untested power cable to clock module. <br /> <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA. <br /> <br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=75 2013-01-16T17:46:15Z

<p>Weizeor: /* COMPLETED TASK */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === With Detector Head from LBNL<br /> <br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=74 2013-01-16T17:45:36Z

<p>Weizeor: /* When Detector Head Arrives from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === With Detector Head from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=73 2013-01-09T15:46:15Z

<p>Weizeor: /* When Detector Head Arrives from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> The plan is to open up the detector head and remove the vacuum cables.<br /> I can then use extra vacuum feed through connectors to test all of the cables to the clock module.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Status&diff=72 2013-01-09T15:40:51Z

<p>Weizeor: </p> <hr /> <div>1-9-2013 Detector Head is sitting outside John's office when he arrives at work<br /> <br /> 1-8-2013 LBL Ships detector Head without buffer chips to APS at noon<br /> <br /> 11-15-2012 Decide to build two more detector heads without buffer chips and ship one to APS so that we could work in parallel to solve some problems and develop code. This will make a total of 4 detector heads.<br /> <br /> 4-3-2012 First x-ray on back illuminated 1K Frame Shift CCD using final hardware configuration.<br /> <br /> 2-29-2012 First light on a back illuminated 1K Frame Shift CCD. The back side used the LBNL in house pizza process.<br /> <br /> 2-29-2012 Plan on using front side 1K FTFCCD to look for noise sources. Suspect bias voltages Vdd or VddRst, which are generated in clock module, may be noisy.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Log_of_Problems_and_Solutions&diff=71 2013-01-09T14:07:34Z

<p>Weizeor: /* SOLVED 2-8-2012 Jitter and Flashing of image */</p> <hr /> <div>== SOLVED 2-8-2012 Jitter and Flashing of 1st column in image==<br /> '''PROBLEM:''' On front illuminated image it was observed that the images had a flashing on the first column and that there was a pixel jitter.<br /> <br /> '''CAUSE:''' The pipeline in the fCRIC must first be purge before we get the real data from the CCD. This is done in state 4 of the readout state machine. After state 4 the readot goes to state 5 where it starts saving data. The state machine was entering state 5 while in the middle of the data transfers started in state 4.<br /> <br /> '''SOLUTION:''' Extend the end time of state 4 from 96 ticks to 245 ticks. This will prevent the system from entering state 5 until the fCRICs are done sending out their data. Since this state is only used for 6 pixles it will not have a signifigant inpact on the total readout time.<br /> <br /> == SOLVED 6-1-2012 Buffer chips could get more than 5V==<br /> '''PROBLEM:''' It was possible through software to apply more than 5V to the buffer chips. This allows developers and users to issue a &quot;Self-Destruct&quot; command. This has been tested out and verified to work. (Too soon to joke?) <br /> <br /> '''SOLUTION:''' Initially there was a Software fix, but a hardware solution was implemented and was included in the final 12 boards.<br /> <br /> == NOT SOLVED YET ==<br /> <br /> Noise and gain not as good as we would like on the prototypes with the buffer chips.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=70 2013-01-08T22:52:46Z

<p>Weizeor: /* When Detector Head Arrives from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> Verify that the noise is at the expected level.<br /> 6. Take some optical images.<br /> Generate a photon transfer curve.<br /> 7. Work on solving miscellaneous problems with LBNL<br /> Optimize configuration parameters<br /> 8. Software development<br /> Area detector, data reduction, user interface.....<br /> 9. Take some Fe and other source images<br /> Will also be used to optimize configuration parameters<br /> 10. Test at the Optics/Detector Beam line<br /> Maybe able to take some flat field measurments?<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=69 2013-01-08T22:50:25Z

<p>Weizeor: </p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images.<br /> Verify that dark images vary with different exposure times.<br /> and that the noise is at the expected level.<br /> 6. Take some optical images. (Generate a photon transfer curve)<br /> 7. Work on solving miscellaneous problems with LBNL<br /> 8. Software development: Area detector, data reduction, user interface.....<br /> 9. Take some Fe source images<br /> 10. Test at the Optics/Detector Beam line<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=68 2013-01-08T22:49:53Z

<p>Weizeor: /* When Detector Head Arrives from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> We found out today that this will require some tools, which are now on order<br /> 4. Wire up equipment protection interlock and test it out<br /> This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images. Verify that dark images vary with different exposure times and that the noise is at the expected level.<br /> 6. Take some optical images. (Generate a photon transfer curve)<br /> 7. Work on solving miscellaneous problems with LBNL<br /> 8. Software development: Area detector, data reduction, user interface.....<br /> 9. Take some Fe source images<br /> 10. Test at the Optics/Detector Beam line<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=67 2013-01-08T22:48:28Z

<p>Weizeor: /* When Detector Head Arrives from LBL */</p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1. Ring out untested power cable to clock module. <br /> The power goes through vacuum cables that are part of the detector head.<br /> 2. Power spare clock module with power cables and test communications with Computer Interface Node (CIN) in ATCA.<br /> This will verify that CIN is working and test all of the clock module cables without endangering the detector.<br /> 3. Install Immersion chiller probe on detector head.<br /> (We found out today that this will require some tools, which are now on order)<br /> 4. Wire up equipment protection interlock and test it out<br /> (This prevents the detector from overheating and prevents the chiller from turning on if there is no vacuum)<br /> 5. Put a vacuum on the detector, cool it down, power it up, take some dark images. Verify that dark images vary with different exposure times and that the noise is at the expected level.<br /> 6. Take some optical images. (Generate a photon transfer curve)<br /> 7. Work on solving miscellaneous problems with LBNL<br /> 8. Software development: Area detector, data reduction, user interface.....<br /> 9. Take some Fe source images<br /> 10. Test at the Optics/Detector Beam line<br /> 11. Install at Beam Lines<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=66 2013-01-08T22:46:54Z

<p>Weizeor: /* TO DO */</p> <hr /> <div>== TO DO ==<br /> <br /> === When Detector Head Arrives from LBL ===<br /> 1.<br /> <br /> <br /> <br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=65 2013-01-08T22:46:08Z

<p>Weizeor: /* Power Supply */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=64 2013-01-08T22:45:43Z

<p>Weizeor: /* Clock Module */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered<br /> <br /> === Power Supply ===<br /> * 12-20-2012 Added connector on back for interlock system. When open power supply turns off.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=63 2013-01-08T22:44:17Z

<p>Weizeor: /* Clock Module */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=62 2013-01-08T22:44:05Z

<p>Weizeor: /* ATCA Shelves */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links<br /> <br /> === Clock Module ===<br /> * 8-1-2012 Shipped 12 tested Clock Modules to LBL <br /> Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module) <br /> Order 2 blank PCB <br /> * 4-2-2012 PCBs ordered (15 days) <br /> * 4-3-2012 Assembly ordered</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=61 2013-01-08T22:43:13Z

<p>Weizeor: /* Chiller System */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=60 2013-01-08T22:43:00Z

<p>Weizeor: /* Chiller */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * Need to install into detector heads<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * Need to be installed into detector heads<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=59 2013-01-08T22:42:31Z

<p>Weizeor: /* Chiller System */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> * Need to be installed into detector heads<br /> * APS has two Systems<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=58 2013-01-08T22:41:08Z

<p>Weizeor: /* ATCA Shelves */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=57 2013-01-08T22:40:53Z

<p>Weizeor: /* COMPLETED TASK */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> <br /> === ATCA Shelves ===<br /> * Arrived from <br /> * Linux installed<br /> * Lots of software installed<br /> * Raid array mounted and tested using 10Gbit Links</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=56 2013-01-08T22:39:04Z

<p>Weizeor: /* GUI */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=55 2013-01-08T22:38:50Z

<p>Weizeor: /* GUI */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=54 2013-01-08T22:38:19Z

<p>Weizeor: /* GUI */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=53 2013-01-08T22:37:30Z

<p>Weizeor: /* GUI */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC Timing waveforms<br /> * Sync/Update Exposure control when other data is sent down<br /> * One button to send file to FPGA and update GUI<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls<br /> * Add fCRIC Timing waveforms <br /> * Sync/Update Exposure control when other data is sent down <br /> * One button to send file to FPGA and update GUI</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=52 2013-01-08T22:36:40Z

<p>Weizeor: /* Clock Module */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *8-1-2012 Shipped 12 tested Clock Modules to LBL<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC Timing waveforms<br /> * Sync/Update Exposure control when other data is sent down<br /> * One button to send file to FPGA and update GUI<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Status&diff=51 2013-01-08T22:31:48Z

<p>Weizeor: </p> <hr /> <div>1-8-2013 LBL Ships detector head without buffer chips to APS<br /> <br /> 11-15-2012 Decide to build two more detector heads without buffer chips and ship one to APS so that we could work in parallel to solve some problems and develop code. This will make a total of 4 detector heads.<br /> <br /> 4-3-2012 First x-ray on back illuminated 1K Frame Shift CCD using final hardware configuration.<br /> <br /> 2-29-2012 First light on a back illuminated 1K Frame Shift CCD. The back side used the LBNL in house pizza process.<br /> <br /> 2-29-2012 Plan on using front side 1K FTFCCD to look for noise sources. Suspect bias voltages Vdd or VddRst, which are generated in clock module, may be noisy.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Log_of_Problems_and_Solutions&diff=50 2013-01-08T22:28:18Z

<p>Weizeor: /* SOLVED 2-8-2012 Jitter and Flashing of image */</p> <hr /> <div>== SOLVED 2-8-2012 Jitter and Flashing of image==<br /> '''PROBLEM:''' On front illuminated image it was observed that the images had a flashing on the first column and that there was a pixel jitter.<br /> <br /> '''CAUSE:''' The pipeline in the fCRIC must first be purge before we get the real data from the CCD. This is done in state 4 of the readout state machine. After state 4 the readot goes to state 5 where it starts saving data. The state machine was entering state 5 while in the middle of the data transfers started in state 4.<br /> <br /> '''SOLUTION:''' Extend the end time of state 4 from 96 ticks to 245 ticks. This will prevent the system from entering state 5 until the fCRICs are done sending out their data. Since this state is only used for 6 pixles it will not have a signifigant inpact on the total readout time.<br /> <br /> == SOLVED 6-1-2012 Buffer chips could get more than 5V==<br /> '''PROBLEM:''' It was possible through software to apply more than 5V to the buffer chips. This allows developers and users to issue a &quot;Self-Destruct&quot; command. This has been tested out and verified to work. (Too soon to joke?) <br /> <br /> '''SOLUTION:''' Initially there was a Software fix, but a hardware solution was implemented and was included in the final 12 boards.<br /> <br /> == NOT SOLVED YET ==<br /> <br /> Noise and gain not as good as we would like on the prototypes with the buffer chips.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Log_of_Problems_and_Solutions&diff=49 2013-01-08T22:24:21Z

<p>Weizeor: /* NOT SOLVED YET - Buffer Chips should not recieve more than +5V */</p> <hr /> <div>== SOLVED 2-8-2012 Jitter and Flashing of image==<br /> '''PROBLEM:''' On front illuminated image it was observed that the images had a flashing on the first column and that there was a pixel jitter.<br /> <br /> '''CAUSE:''' The pipeline in the fCRIC must first be purge before we get the real data from the CCD. This is done in state 4 of the readout state machine. After state 4 the readot goes to state 5 where it starts saving data. The state machine was entering state 5 while in the middle of the data transfers started in state 4.<br /> <br /> '''SOLUTION:''' Extend the end time of state 4 from 96 ticks to 245 ticks. This will prevent the system from entering state 5 until the fCRICs are done sending out their data. Since this state is only used for 6 pixles it will not have a signifigant inpact on the total readout time.<br /> <br /> '''PROBLEM:''' It was possible through software to apply more than 5V to the buffer chips. This allows developers and users to issue a &quot;Self-Destruct&quot; command. This has been tested out and verified to work. (Too soon to joke?) <br /> <br /> '''SOLUTION:''' Initially there was a Software fix, but a hardware solution should was implemented and was included in the final 12 boards.<br /> <br /> == NOT SOLVED YET ==<br /> <br /> Noise and gain not as good as we would like on the prototypes with the buffer chips.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Log_of_Problems_and_Solutions&diff=48 2013-01-08T22:23:23Z

<p>Weizeor: /* SOLVED 2-8-2012 Jitter and Flashing of image */</p> <hr /> <div>== SOLVED 2-8-2012 Jitter and Flashing of image==<br /> '''PROBLEM:''' On front illuminated image it was observed that the images had a flashing on the first column and that there was a pixel jitter.<br /> <br /> '''CAUSE:''' The pipeline in the fCRIC must first be purge before we get the real data from the CCD. This is done in state 4 of the readout state machine. After state 4 the readot goes to state 5 where it starts saving data. The state machine was entering state 5 while in the middle of the data transfers started in state 4.<br /> <br /> '''SOLUTION:''' Extend the end time of state 4 from 96 ticks to 245 ticks. This will prevent the system from entering state 5 until the fCRICs are done sending out their data. Since this state is only used for 6 pixles it will not have a signifigant inpact on the total readout time.<br /> <br /> '''PROBLEM:''' It was possible through software to apply more than 5V to the buffer chips. This allows developers and users to issue a &quot;Self-Destruct&quot; command. This has been tested out and verified to work. (Too soon to joke?) <br /> <br /> '''SOLUTION:''' Initially there was a Software fix, but a hardware solution should was implemented and was included in the final 12 boards.<br /> <br /> == NOT SOLVED YET - Buffer Chips should not recieve more than +5V==<br /> '''PROBLEM''' It is possible through software to apply more than 5V to the buffer chips. This allows developers and users to issue a &quot;Self-Destruct&quot; command. This has been tested out and verified to work. (Too soon to joke?)<br /> <br /> '''SOLUTION''' Software protection has been implemented in the GUI, but a hardware solution should be implemented.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Fast_CCD_Detector&diff=47 2012-09-26T22:02:35Z

<p>Weizeor: /* Soft Glue Logic to Control the Tuning Fork Shutter at 8id */</p> <hr /> <div>== Overview and History of the Fast CCD Detectors ==<br /> <br /> At a SPIE Conference in 2005 (International Society for Optical Engineering) Howard Padmore gave talk called &quot;Fast CCD-Based systems for detection of x-ray and electronics&quot; based on custom CCDs designed at LBNL. Steve Ross attended the talk and meet with Howard after the presentation and discussed the possibility of collaborating with LBNL in the development and fabrication of a x-ray detectors based on these fast readout CCD chips. During meetings held in October and December of 2005 it was decided that LBNL and APS would work together to develop these x-ray detectors. The first detector, now in use, is called the 480 Fast CCD Detector. The second generation detector, currently under development, uses a 1920 x 960 CCD developed by LBNL. It can be operated as a 960 x 960 frame shift Fast CCD. The first and second generation Fast CCD sensors, developed at LBNL, are based on 10 columns per output. The third generation Fast CCD will have a fully column parallel readout, where each column has their own output.<br /> <br /> Collaborators:<br /> <br /> LBNL - Nord Adresen, Brad Bingham, Devis Contarato, Peter Denes, Dionisio Doering, John Joseph, Patrick McVittie<br /> <br /> ANL - Jonathan Baldwin, Tim Madden, Suresh Narayanan, Alec Sandy, Emil Trakhtenberg, John Weizeorick<br /> <br /> [[File:ARRA-camera-8556m_350x389.jpg|frame|center|1K Frame Shift Fast CCD Assembly]]<br /> [[File:FastCCD1_300x313.jpg|frame|center|480 Fast CCD at APS]]<br /> <br /> == Presentations and Publications ==<br /> <br /> '''Presentations'''<br /> <br /> '''Publications'''<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v82/i7/p073303_s1?view=fulltext Development of a compact fast CCD camera and resonant soft x-ray scatterning endstation for time-resolved pump-probe experements] <br /> AIP Review of Scientific Instruments (Vol. 82 Issue 7)<br /> <br /> [http://www.aps.anl.gov/Xray_Science_Division/Detectors/Development/FCCD/Docs/NIMA52814.pdf Real-time compression of streaming X-ray photon correlation spectroscopy area-detector data] Nuclear Instruments and Methods in Physical Research A (649 (2011) 237-239)<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v80/i8/p083302_s1 A fast, direct x-ray detection charge-couple device] Review of Scientific Instruments (Vol.80, Issue 8)<br /> <br /> == 1K Frame Shift CCD Detector ==<br /> <br /> === [[To Do List]] ===<br /> <br /> === [[Status]] ===<br /> <br /> === [[Log of Problems and Solutions]] ===<br /> <br /> === [[List of configuration files]] ===<br /> <br /> == 480 Fast CCD Detector ==<br /> <br /> === Soft Glue Logic to Control the Tuning Fork Shutter at 8id ===<br /> *[[Media:Soft_Glue_Logic_for_tuning_fork_shutter_at_8id.docx]]<br /> <br /> == Fully Column Parallel Fast CCD Detector ==</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=File:Soft_Glue_Logic_for_tuning_fork_shutter_at_8id.docx&diff=46 2012-09-26T22:01:41Z

<p>Weizeor: </p> <hr /> <div></div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Fast_CCD_Detector&diff=45 2012-04-18T21:19:45Z

<p>Weizeor: /* Soft Glue Logic to Control the Tuning Fork Shutter at 8id */</p> <hr /> <div>== Overview and History of the Fast CCD Detectors ==<br /> <br /> At a SPIE Conference in 2005 (International Society for Optical Engineering) Howard Padmore gave talk called &quot;Fast CCD-Based systems for detection of x-ray and electronics&quot; based on custom CCDs designed at LBNL. Steve Ross attended the talk and meet with Howard after the presentation and discussed the possibility of collaborating with LBNL in the development and fabrication of a x-ray detectors based on these fast readout CCD chips. During meetings held in October and December of 2005 it was decided that LBNL and APS would work together to develop these x-ray detectors. The first detector, now in use, is called the 480 Fast CCD Detector. The second generation detector, currently under development, uses a 1920 x 960 CCD developed by LBNL. It can be operated as a 960 x 960 frame shift Fast CCD. The first and second generation Fast CCD sensors, developed at LBNL, are based on 10 columns per output. The third generation Fast CCD will have a fully column parallel readout, where each column has their own output.<br /> <br /> Collaborators:<br /> <br /> LBNL - Nord Adresen, Brad Bingham, Devis Contarato, Peter Denes, Dionisio Doering, John Joseph, Patrick McVittie<br /> <br /> ANL - Jonathan Baldwin, Tim Madden, Suresh Narayanan, Alec Sandy, Emil Trakhtenberg, John Weizeorick<br /> <br /> [[File:ARRA-camera-8556m_350x389.jpg|frame|center|1K Frame Shift Fast CCD Assembly]]<br /> [[File:FastCCD1_300x313.jpg|frame|center|480 Fast CCD at APS]]<br /> <br /> == Presentations and Publications ==<br /> <br /> '''Presentations'''<br /> <br /> '''Publications'''<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v82/i7/p073303_s1?view=fulltext Development of a compact fast CCD camera and resonant soft x-ray scatterning endstation for time-resolved pump-probe experements] <br /> AIP Review of Scientific Instruments (Vol. 82 Issue 7)<br /> <br /> [http://www.aps.anl.gov/Xray_Science_Division/Detectors/Development/FCCD/Docs/NIMA52814.pdf Real-time compression of streaming X-ray photon correlation spectroscopy area-detector data] Nuclear Instruments and Methods in Physical Research A (649 (2011) 237-239)<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v80/i8/p083302_s1 A fast, direct x-ray detection charge-couple device] Review of Scientific Instruments (Vol.80, Issue 8)<br /> <br /> == 1K Frame Shift CCD Detector ==<br /> <br /> === [[To Do List]] ===<br /> <br /> === [[Status]] ===<br /> <br /> === [[Log of Problems and Solutions]] ===<br /> <br /> === [[List of configuration files]] ===<br /> <br /> == 480 Fast CCD Detector ==<br /> <br /> === Soft Glue Logic to Control the Tuning Fork Shutter at 8id ===<br /> *[[Media:SoftGlueLogic.docx]]<br /> <br /> == Fully Column Parallel Fast CCD Detector ==</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=44 2012-04-18T21:19:14Z

<p>Weizeor: /* Clock Module */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> *4-2-2012 PCBs ordered (15 days)<br /> *4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC Timing waveforms<br /> * Sync/Update Exposure control when other data is sent down<br /> * One button to send file to FPGA and update GUI<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Status&diff=43 2012-04-18T21:18:00Z

<p>Weizeor: </p> <hr /> <div>4-3-2012 First x-ray on back illuminated 1K Frame Shift CCD using final hardware configuration.<br /> <br /> 2-29-2012 First light on a back illuminated 1K Frame Shift CCD. The back side used the LBNL in house pizza process.<br /> <br /> 2-29-2012 Plan on using front side 1K FTFCCD to look for noise sources. Suspect bias voltages Vdd or VddRst, which are generated in clock module, may be noisy.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Status&diff=42 2012-04-18T21:17:26Z

<p>Weizeor: </p> <hr /> <div>4-3-2012 First x-ray on back illuminated 1K Frame Shift CCD using final hardware configuration. <br /> 2-29-2012 First light on a back illuminated 1K Frame Shift CCD. The back side used the LBNL in house pizza process.<br /> <br /> 2-29-2012 Plan on using front side 1K FTFCCD to look for noise sources. Suspect bias voltages Vdd or VddRst, which are generated in clock module, may be noisy.</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Fast_CCD_Detector&diff=41 2012-04-18T21:15:47Z

<p>Weizeor: /* Soft Glue Logic to Control the Tuning Fork Shutter at 8id */</p> <hr /> <div>== Overview and History of the Fast CCD Detectors ==<br /> <br /> At a SPIE Conference in 2005 (International Society for Optical Engineering) Howard Padmore gave talk called &quot;Fast CCD-Based systems for detection of x-ray and electronics&quot; based on custom CCDs designed at LBNL. Steve Ross attended the talk and meet with Howard after the presentation and discussed the possibility of collaborating with LBNL in the development and fabrication of a x-ray detectors based on these fast readout CCD chips. During meetings held in October and December of 2005 it was decided that LBNL and APS would work together to develop these x-ray detectors. The first detector, now in use, is called the 480 Fast CCD Detector. The second generation detector, currently under development, uses a 1920 x 960 CCD developed by LBNL. It can be operated as a 960 x 960 frame shift Fast CCD. The first and second generation Fast CCD sensors, developed at LBNL, are based on 10 columns per output. The third generation Fast CCD will have a fully column parallel readout, where each column has their own output.<br /> <br /> Collaborators:<br /> <br /> LBNL - Nord Adresen, Brad Bingham, Devis Contarato, Peter Denes, Dionisio Doering, John Joseph, Patrick McVittie<br /> <br /> ANL - Jonathan Baldwin, Tim Madden, Suresh Narayanan, Alec Sandy, Emil Trakhtenberg, John Weizeorick<br /> <br /> [[File:ARRA-camera-8556m_350x389.jpg|frame|center|1K Frame Shift Fast CCD Assembly]]<br /> [[File:FastCCD1_300x313.jpg|frame|center|480 Fast CCD at APS]]<br /> <br /> == Presentations and Publications ==<br /> <br /> '''Presentations'''<br /> <br /> '''Publications'''<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v82/i7/p073303_s1?view=fulltext Development of a compact fast CCD camera and resonant soft x-ray scatterning endstation for time-resolved pump-probe experements] <br /> AIP Review of Scientific Instruments (Vol. 82 Issue 7)<br /> <br /> [http://www.aps.anl.gov/Xray_Science_Division/Detectors/Development/FCCD/Docs/NIMA52814.pdf Real-time compression of streaming X-ray photon correlation spectroscopy area-detector data] Nuclear Instruments and Methods in Physical Research A (649 (2011) 237-239)<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v80/i8/p083302_s1 A fast, direct x-ray detection charge-couple device] Review of Scientific Instruments (Vol.80, Issue 8)<br /> <br /> == 1K Frame Shift CCD Detector ==<br /> <br /> === [[To Do List]] ===<br /> <br /> === [[Status]] ===<br /> <br /> === [[Log of Problems and Solutions]] ===<br /> <br /> === [[List of configuration files]] ===<br /> <br /> == 480 Fast CCD Detector ==<br /> <br /> === Soft Glue Logic to Control the Tuning Fork Shutter at 8id ===<br /> [[Media:SoftGlueLogic.docx]]<br /> <br /> == Fully Column Parallel Fast CCD Detector ==</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=File:SoftGlueLogic.docx&diff=40 2012-04-18T21:10:46Z

<p>Weizeor: Document describing the soft glue used to control the tuning fork shutter and scyronize the exposures of the 480 FCCD detector</p> <hr /> <div>Document describing the soft glue used to control the tuning fork shutter and scyronize the exposures of the 480 FCCD detector</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=Fast_CCD_Detector&diff=39 2012-04-18T21:07:54Z

<p>Weizeor: /* Soft Glue Logic to Control the Tuning Fork Shutter at 8id */</p> <hr /> <div>== Overview and History of the Fast CCD Detectors ==<br /> <br /> At a SPIE Conference in 2005 (International Society for Optical Engineering) Howard Padmore gave talk called &quot;Fast CCD-Based systems for detection of x-ray and electronics&quot; based on custom CCDs designed at LBNL. Steve Ross attended the talk and meet with Howard after the presentation and discussed the possibility of collaborating with LBNL in the development and fabrication of a x-ray detectors based on these fast readout CCD chips. During meetings held in October and December of 2005 it was decided that LBNL and APS would work together to develop these x-ray detectors. The first detector, now in use, is called the 480 Fast CCD Detector. The second generation detector, currently under development, uses a 1920 x 960 CCD developed by LBNL. It can be operated as a 960 x 960 frame shift Fast CCD. The first and second generation Fast CCD sensors, developed at LBNL, are based on 10 columns per output. The third generation Fast CCD will have a fully column parallel readout, where each column has their own output.<br /> <br /> Collaborators:<br /> <br /> LBNL - Nord Adresen, Brad Bingham, Devis Contarato, Peter Denes, Dionisio Doering, John Joseph, Patrick McVittie<br /> <br /> ANL - Jonathan Baldwin, Tim Madden, Suresh Narayanan, Alec Sandy, Emil Trakhtenberg, John Weizeorick<br /> <br /> [[File:ARRA-camera-8556m_350x389.jpg|frame|center|1K Frame Shift Fast CCD Assembly]]<br /> [[File:FastCCD1_300x313.jpg|frame|center|480 Fast CCD at APS]]<br /> <br /> == Presentations and Publications ==<br /> <br /> '''Presentations'''<br /> <br /> '''Publications'''<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v82/i7/p073303_s1?view=fulltext Development of a compact fast CCD camera and resonant soft x-ray scatterning endstation for time-resolved pump-probe experements] <br /> AIP Review of Scientific Instruments (Vol. 82 Issue 7)<br /> <br /> [http://www.aps.anl.gov/Xray_Science_Division/Detectors/Development/FCCD/Docs/NIMA52814.pdf Real-time compression of streaming X-ray photon correlation spectroscopy area-detector data] Nuclear Instruments and Methods in Physical Research A (649 (2011) 237-239)<br /> <br /> [http://rsi.aip.org/resource/1/rsinak/v80/i8/p083302_s1 A fast, direct x-ray detection charge-couple device] Review of Scientific Instruments (Vol.80, Issue 8)<br /> <br /> == 1K Frame Shift CCD Detector ==<br /> <br /> === [[To Do List]] ===<br /> <br /> === [[Status]] ===<br /> <br /> === [[Log of Problems and Solutions]] ===<br /> <br /> === [[List of configuration files]] ===<br /> <br /> == 480 Fast CCD Detector ==<br /> <br /> === [[Soft Glue Logic to Control the Tuning Fork Shutter at 8id]] ===<br /> [[Media:SoftGlueLogic.docx]]<br /> <br /> == Fully Column Parallel Fast CCD Detector ==</div>

Weizeor https://wiki-ext.aps.anl.gov/ccd/index.php?title=To_Do_List&diff=38 2012-04-18T21:04:38Z

<p>Weizeor: /* Clock Module */</p> <hr /> <div>== TO DO ==<br /> <br /> === CIN Modules ===<br /> * LBNL to fill in?<br /> <br /> === Clock Module ===<br /> *Need to fully build 12 Clock Modules, LBNL will provide metal plates (3 per module)<br /> *Order 2 blank PCB<br /> 4-2-2012 PCBs ordered (15 days)<br /> 4-3-2012 Assembly ordered<br /> <br /> === Top Module ===<br /> * LBNL to fill in<br /> <br /> === Digitizer Module ===<br /> * LBNL to fill in<br /> <br /> === Chiller ===<br /> * LBNL needs to build custom flex-cool probe heads and send to FTS Systems<br /> <br /> === Power Supply ===<br /> <br /> === ATCA Shelves ===<br /> *APS still waiting for 2 from Shelves from ZNYX.<br /> <br /> === GUI ===<br /> * Add fCRIC Timing waveforms<br /> * Sync/Update Exposure control when other data is sent down<br /> * One button to send file to FPGA and update GUI<br /> * Add fCRIC mask to GUI<br /> * Currenly when you send down a configuration file it does not update the GUI's waveforms, and bias windows, unless you are in the the waveform or bias window.<br /> * Allow user to choose which waveforms to view (will need when fCRIC waveforms are added)<br /> * Keep consolidating redundant routines<br /> <br /> <br /> == COMPLETED TASK ==<br /> <br /> === Vacuum Chambers ===<br /> *APS has two vacuum chambers built<br /> <br /> === Chiller System ===<br /> *LBNL has finished chiller system design and is in the process of building the flex-cool custom probe heads.<br /> *APS has started the process to order two systems.<br /> <br /> === GUI ===<br /> * Put under CVS control<br /> * Added image viewer<br /> * Added Expousre controls</div>

Weizeor